1. Technical Field
The present invention is related to phase-locked loops (PLLs) and the voltage-controlled oscillators (VCOs) used in phase-locked loops. More specifically, the present invention is directed toward a VCO and PLL that separate the error/control voltages into AC and DC components, so as to prevent AC noise currents emanating from the VCO output from interfering with the DC error/control voltage determining the frequency of the VCO.
2. Description of Related Art
A high frequency voltage controlled oscillator (VCO) is extremely important for applications such as processor clock generation and distribution, wired and wireless communication, system synchronization and frequency synthesis. Research on VCOs for the past decade has been concentrated in the areas of raising the frequency, reducing jitter, lowering the operating voltage and power, and increasing the frequency tuning range. Often these design goals are achieved only at the expense of some or all of the other performance objectives.
High frequency analog VCOs operating with current sources may have signal amplitudes that are only a small fraction of the supply voltage, severely limiting their usefulness. Current starved ring oscillators using three or four levels of cascading have become quite common, but they are extremely noise sensitive because of their very high gain, are inherently nonlinear (especially near cutoff where they often stop oscillating), are sensitive to fabrication process and operating environments, and exhibit excessive jitter characteristics. Delay interpolating oscillators are capable of very low jitter due to low gain and low noise sensitivity, but they are inherently limited in frequency range and are difficult to build in less than four levels. Multiphase oscillators offer advantages by pipelining operations using equally spaced phases at lower frequencies, but control mechanisms in delay interpolators introduce offsets from the ideal phase spacing. Inductive-capacitive (LC) oscillators are capable of high frequency and extremely low jitter but are difficult to integrate and model, and also have tuning ranges of only a few percent.
An interleaved oscillator structure described in co-pending U.S. patent application Ser. No. 09/726,282, entitled xe2x80x9cHigh-Frequency Low-Voltage Multiphase Voltage-Controlled Oscillatorxe2x80x9d and co-pending U.S. patent application Ser. No. 09/726,285, entitled xe2x80x9cMultiphase Voltage Controlled Oscillator with Variable Gain and Rangexe2x80x9d eliminates many of the problems described above. This oscillator structure, however, is limited in its application, since the topology generates noise currents. These noise currents prevent the oscillator structure from being used in conventional phase-locked loop (PLL) clock generators for low jitter applications. Therefore, a VCO topology and PLL implementation that exhibit the advantages of the aforementioned interleaved VCO topology, but that allow for low-jitter operation are needed.
The present invention provides voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
In a preferred embodiment, the VCO utilizes a multiphase interleaved feedforward topology, wherein the feedforward paths are bifurcated into a low AC-impedance path and a DC path. The low AC-impedance path is controlled by the AC-component control input, and the DC path is controlled by the DC-component control input. In this way, AC noise currents are prevented from interfering with the DC control voltage and operating point of the oscillator.